Current technology employs stacking semiconductor chips (e.g., microprocessors, digital signal processors, etc.) or arranging the chips side-by-side. Communication between the chips is sometimes achieved by connecting them using bond wires that hang loose outside of the die space of the chips. Other embodiments use Through Silicon Vias (TSVs) instead of, or in addition to, bond wires. Bond wires, TSVs, and the like are generally referred to as “interconnects.”
As die stacks use more and more interconnects, issues of failure and yield are presented. For instance, if a failure rate for a particular high-density interconnect is one in one thousand, and there are one thousand of the high-density interconnects in each device, then on average every device should experience an interconnect failure. Such a low yield is generally considered to be unacceptable.
In the area of computer-readable memory, redundant memory cells have been used to ameliorate the problem of failed cells. In some example conventional memory chips, there is a built in self repair facility that tests memory units in the chip for operability. When one or more units are found to be defective, the built in self repair facility “repairs” the chip by directing data that would otherwise be stored in the defective unit to one or more other redundant units. In contrast to the technique used in memory chips, there is currently no effective way to compensate for failures in high-density interconnects.